Electronic components such as semiconductor chips are mounted on wiring substrates of various shapes and structures. Semiconductor chips have become highly sophisticated. Further, semiconductor chips are mounted on wiring substrates in larger scales of integration. As a result, the demand for finer wiring has increased in wiring substrates on which semiconductor chips are mounted.
Japanese Laid-Out Patent Publication No. 2001-110836 describes a wiring substrate in which a wiring pattern is formed on an outermost insulation layer and metal posts are formed on the wiring pattern. In the wiring substrate, a resin layer is formed on the upper surface of the outermost insulation layer to cover the entire surface of the wiring pattern and part of the side surface of each metal post. The upper end of each post is exposed from the resin layer. The upper surface of the resin layer is flat.
In the wiring substrate, a surface-processed layer is formed on the portion of each metal post exposed from the resin layer to improve the corrosion resistance of the metal post. When, for example, flip-chip-connecting a solder layer of a semiconductor chip to the metal post, the surface-processed layer improves the connecting properties of the metal post and a solder layer. However, when the level of adhesion is low between the surface-processed layer and the resin layer, a gap may be formed between the lower surface of the surface-processed layer and the upper surface of the resin layer. When such a gap is formed, the molten solder layer may enter the gap when the flip-chip connection is performed. When solder enters the gap, electromigration occurs between the metal post and the solder layer. This lowers the connection reliability of the solder layer with respect to the metal post and the surface-processed layer.